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| a FEATURES IF Subsystem Bandpass Modulator Variable-Gain Preamplifier with 13 dB of AGC Range Mixer AGC Detector Op Amp for LNA Biasing ECL-to-CMOS Level Translator Ultralow Power Design 2.7 V Operating Voltage 4.8 mA Current Consumption Power-Down Control Small 20-Lead SSOP Package APPLICATIONS FLEXTM, ReFLEXTM Receivers Multimode Receivers Bandpass GENERAL DESCRIPTION IF Subsystem AD6140 The AD6140 is a bandpass ADC IF IC for receivers requiring a high dynamic range and multiple filter bandwidths. With an external decimation filter, it creates a multibit analog-to-digital converter. The AD6140 consists of a variable gain, low noise preamplifier, mixer, AGC detector, bandpass modulator, an ECL-to-CMOS level translator for the system clock, and an auxiliary amplifier for use in biasing a discrete LNA. It is designed to operate with Motorola's ReFLEX chipset solution. Contact Motorola directly for more information about the ReFLEX chipset solution. With data and clock outputs at CMOS logic levels, it interfaces to an external decimation filter. It comes in a 20-lead plastic SSOP and operates over the -40C to +85C industrial temperature range at 2.7 V. FUNCTIONAL BLOCK DIAGRAM LO_IN+ LO_IN- MIXER POST AMPLIFIER AD6140 _DATA_OUT MODULATOR _CLOCK_OUT PREAMPLIFIER IF_INPUT LNA_SENSE LNA_FORCE LNA BIAS AMPLIFIER MIXER AGC DETECTOR CIRCUIT ECL-TO-CMOS LEVEL-SHIFTER BUFFER_VDD CLK_IN+ CLK_IN- AGC_CAPACITOR 0.1 F AGC_TC_SELECT BIAS SYSTEM BUFFER_GND VOLTAGE_REFERENCE_IN RINT AVDD AGND DGND DVDD POWER_DOWN BIAS_RESISTOR 39k FLEX and ReFLEX are trademarks of Motorola, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998 AD6140-SPECIFICATIONS (T = +25 C, V A CC = 2.7 V, VOLTAGE_REFERENCE_IN = 1 V, unless otherwise noted) Min Typ Max Units Specification OVERALL Conditions VOLTAGE_REFERENCE_IN = 1 V 5% dc, IF = 49.6 MHz LO = 49.792 MHz or 49.408 MHz, 200 mV p-p Differential Input Clock = 6.144 MHz, 800 mV p-p Differential ECL Input, Clock Asymmetry = 50 2.5% At Max Gain At Max Gain, External Termination At IF_INPUT (Pin 19) At IF_INPUT (Pin 19) 6.25 kHz Bandwidth Centered at 192 kHz Input Third Order Intercept Point Noise Figure Input Resistance Input Capacitance Dynamic Range Maximum Gain Minimum Gain AGC DETECTOR AGC Threshold Capacitor Charging Current ECL-TO-CMOS LEVEL TRANSLATOR Clock Output Drive Clock Asymmetry LNA BIAS AMPLIFIER VOLTAGE LNA_FORCE LNA_SENSE Input Voltage Range POWER-DOWN INTERFACE Logic Threshold Turn-On Response Time Turn-Off Response Time POWER SUPPLY Supply Voltage Supply Current Power-Down Current Operating Temperature Range Specifications subject to change without notice. -27 76 -19 10.5 2.5 12 83 29.5 16 -24 2.8 50 dBm dB k pF dB dB dB dBm A nA AGC_TC_SELECT Input = Logic LOW (FAST AGC) AGC_TC_SELECT Input = Logic HIGH (SLOW AGC) VDD (to VDD - 0.8 V) Differential Levels 5 pF Load 5 pF Load 2.9 V LNA_SENSE, Minimum Gain 2.6 2.5 1.7 VDD 0.7 100 100 2.5 2.9 5.75 +85 V p-p % V V V s s V mA A C VDD - 0.3 To Valid Data Output To Typical Power-Down Supply Current Power-Down Input: Logic LOW = ON, IF_Input = 0 V Power-Down Input: Logic HIGH = OFF -40 4.8 3 -2- REV. 0 AD6140 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION 20 AVDD 19 IF INPUT 18 AGND 17 VOLTAGE REFERENCE IN Supply Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . +5.5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 50 mW Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering (60 sec) . . . . . . . . . . . . +300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 20-Lead SSOP: JA = 126C/W. LNA FORCE 1 LNA SENSE 2 CLK IN+ 3 CLK IN- 4 BUFFER GND 5 DATA OUT 6 AD6140 16 BIAS RESISTOR TOP VIEW 15 LO IN- (Not to Scale) 14 LO IN+ CLOCK OUT 7 BUFFER VDD 8 POWER DOWN 9 AGC TC SELECT 10 13 AGC CAPACITOR 12 DGND 11 DVDD ORDERING GUIDE Model AD6140ARS AD6140ARSRL Temperature Range -40C to +85C -40C to +85C Package Description Shrink Small Outline Package 20-Lead Plastic SSOP on Tape-and-Reel Package Option RS-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6140 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- AD6140 PIN FUNCTION DESCRIPTION Pin No 1 2 3 Pin Name LNA_FORCE LNA_SENSE CLK_IN+ Function Output For Biasing Discrete LNA Input For Biasing Discrete LNA Positive 6.144 MHz ADC Clock Input Applicable Signal Levels Output Ranges from 0 V (LNA OFF) to 2.7 V VDD to VDD - 0.3 V Input 800 mV p-p Differential Input VDD to VDD - 0.8 V Levels Direct Coupled into 1500 Impedance 800 mV p-p Differential Input VDD to VDD - 0.8 V Levels Direct Coupled into 1500 Impedance Pin Connected to Ground CMOS Logic Levels CMOS Logic Levels Digital Supply Input CMOS Logic Levels; 0 V = ON, VPOS = OFF CMOS Logic Levels; 0 V = Fast Mode, VPOS = Slow Mode 4 CLK_IN- Negative 6.144 MHz ADC Clock Input 5 6 7 8 9 10 BUFFER_GND _DATA_OUT _CLOCK_OUT BUFFER_VDD POWER_DOWN AGC_TC_SELECT 11 12 13 14 15 16 17 18 19 20 DVDD DGND AGC_CAPACITOR LO_IN+ LO_IN- BIAS_RESISTOR VOLTAGE_REFERENCE_IN AGND IF_INPUT AVDD ECL-to-CMOS Level Translator Ground ADC Serial Data Output 6.144 MHz ADC Clock Output ECL-to-CMOS Level Translator VDD Turns IC Off and On AGC Time Constant Select; Changes AGC Capacitor Charging Current by 56:1, where FAST AGC Current is 56x SLOW AGC Current Digital Power Supply Input Digital Ground Charge/Discharge Current into AGC Integrator Capacitor Positive LO Input Negative LO Input Resistor to Ground Sets Overall Bias Current and Power Consumption ADC Voltage Reference Input Analog Ground IF Input Analog Power Supply Input Pin Connected to Digital Supply Pin Connected to Ground AGC Integration Capacitor Connected to Ground 200 mV p-p Differential Input; Internally AC-Coupled into 1500 Impedance 200 mV p-p Differential Input, Internally AC-Coupled into 1500 Impedance 39 k Resistor Connected to Ground Regulated and Filtered 1.0 V 5% Input Pin Connected to Ground Typically 16.4 V p-p to 65.2 mV p-p Pin Connected to Analog Supply -4- REV. 0 Typical Performance Characteristics-AD6140 12 VCC = +2.7V 11 NOISE FIGURE - dB -19.5 INPUT IP3 - dBm -19.0 -18.5 -18.0 -17.5 -21.0 -20.5 -20.0 10 9 -17.0 -16.5 8 -16.0 -40 -20 25 60 TEMPERATURE - C 85 -40 25 TEMPERATURE - C 85 Figure 1. Noise Figure vs. Temperature Figure 4. Input IP3 vs. Temperature 12.0 T = +25 C 60 50 11.5 NOISE FIGURE - dB 40 SNR - dB 11.0 30 20 10.5 \ 10 - 90 - 80 - 70 - 60 - 50 - 40 - 30 -120 -112 -108 -100 2.5 2.6 2.7 2.8 SUPPLY VOLTAGE - Volts 2.9 IF INPUT LEVEL - dBm Figure 2. Noise Figure vs. Power Supply Figure 5. Signal to Noise Ratio vs. IF Input Level at TA = +25C -19.20 4.9 -19.25 -19.30 VCC = +2.7V INPUT IP3 - dBm -19.35 -19.40 -19.45 -19.50 -19.55 -19.60 -19.65 2.5 2.6 2.7 2.8 SUPPLY VOLTAGE - Volts 2.9 4.7 -40 -20 25 60 TEMPERATURE - C 85 CURRENT - mA 4.8 Figure 3. Input IP3 vs. Power Supply Figure 6. Supply Current vs. Temperature REV. 0 -5- - 23 -19 10.0 0 AD6140 5.2 TA = +25 C 5.0 OUTPUT LEVEL - dB 0 CURRENT - mA -50 4.8 -100 4.6 RESPONSE FROM 0kHz TO (f S /2)kHz 4.4 2.5 2.6 2.7 2.8 POWER SUPPLY VOLTAGE - Volts 2.9 -150 0 500 1000 1500 2000 2500 FREQUENCY - kHz 3000 3500 Figure 7. Supply Current vs. Power Supply Voltage Figure 9. Output Spectrum of AD6140 PRODUCT OVERVIEW A modulator uses feedback around a low noise quantizer (1 bit in this case) in order to "shape" the spectrum of quantization noise. Using this technique, we can shape noise away from an arbitrary passband, within which we can place a modulated signal. A modulator reproduces the input, but adds quantization noise, which can be digitally removed with a filter, known as a decimation filter. Applying this technique to bandpass signals results in an analog-to-digital converter suitable for converting the IF signals in a digital radio. The output of the AD6140's modulator is shown in Figure 9. As can be seen, the noise is shaped away from a narrow bandwidth, within which we place a signal (a sine wave in this case) resulting in a narrowband, high dynamic range digital representation of the analog input. MODULATION The AD6140 is a bandpass analog-to-digital converter IF IC for dual conversion receivers requiring a high dynamic range and multiple filter bandwidths. It consists of a variable gain, low noise preamplifier, mixer, automatic gain control (AGC) detector, bandpass modulator, an ECL to CMOS level translator and an auxiliary amplifier for use in biasing a discrete LNA. The low noise preamplifier accepts a first IF input at 49.6 MHz from 16.4 V p-p to 63.2 mV p-p. It provides a variable gain from 12 dB to 25 dB. The mixer accepts an LO frequency of 49.792 MHz or 49.408 MHz, resulting in an IF frequency of 192 kHz. The LO level should be 200 mV p-p differential. It is ac-coupled to the AD6140. The mixer operates in the linear region, hence the gain of the mixer is a function of the LO level. As a result, special care must be taken to ensure that the LO level is 200 mV p-p, LO_IN+ LO_IN- MIXER POST AMPLIFIER AD6140 _DATA_OUT MODULATOR _CLOCK_OUT PREAMPLIFIER IF_INPUT LNA_SENSE LNA_FORCE LNA BIAS AMPLIFIER MIXER AGC DETECTOR CIRCUIT ECL-TO-CMOS LEVEL-SHIFTER BUFFER_VDD CLK_IN+ CLK_IN- AGC_CAPACITOR 0.1 F AGC_TC_SELECT BIAS SYSTEM BUFFER_GND VOLTAGE_REFERENCE_IN RINT AVDD AGND DGND DVDD POWER_DOWN BIAS_RESISTOR 39k Figure 8. Functional Block Diagram -6- REV. 0 AD6140 otherwise, the expected gain will not be obtained from the AD6140. In addition to the mixer, there is a mixer postamplifier within the AD6140. The total gain from the mixer and mixer post-amplifier is 5 dB. The modulator uses a 6.144 MHz clock, which is a differential ECL input. There is an ECL-to-CMOS converter on the AD6140, which converts this differential ECL input into a single-ended CMOS signal. This 6.144 MHz single-ended CMOS clock is provided at Pin 7 (_CLOCK_OUT). The output data of the AD6140 is a 6.144 MHz single bitstream at Pin 6 (_DATA_OUT). The signal gain through the modulator is -0.77 dB. Within the modulator, the data output digital bitstream is fed through a 1-bit D/A converter and is fed back to numerous internal points. The level of this feedback signal, known as the full-scale level, defines the modulator input signal level, which would result in the output digital bitstream containing the maximum number of ones possible. This condition, known as maximum ones density, represents the maximum in-band output signal power of the modulator. The full-scale level is set to 2 V p-p or -4.77 dBm (relative to 1500 ). However, if a signal into the modulator is -4.77 dBm, the modulator will enter an unstable state. Consequently, the maximum input to the modulator is constrained to 5 dB less than the signal, which would produce maximum ones density. This level, defined as the clip level, is -9.77 dBm (relative to 1500 ). The maximum signal into the modulator does not correspond to maximum ones density. The entire dynamic range of the resulting analog to digital converter ( modulator plus decimation filter) is not realized. In order to relate the maximum signal into the modulator to the maximum signal out of the modulator, a gain of 5 dB should be applied in the decimation filter. As can be seen in Figure 5, the output signal to noise ratio will increase until a point at which it rapidly degrades. This point represents the input signal level where the modulator has become unstable. As a result, the maximum input signal level is constrained by the point at which it is so high that instability occurs in the modulator. Dynamic range is defined as the difference between the integrated noise floor (within a particular bandwidth) and the power in the output signal just before the modulator has become unstable. For a typical 6.25 kHz bandwidth centered around 192 kHz, the AD6140 has 83 dB of dynamic range. In order to increase the range of useful input signals of the AD6140, an AGC detector is employed which senses the input signal level to the modulator and adjusts the gain in the preamplifier. The AGC circuitry provides 13 dB of automatic gain control range. The AGC operates when the internal AGC voltage is between 700 mV (minimum gain) and 1.55 V (maximum gain). This voltage can be measured on the AGC_CAPACITOR pin (Pin 13). The AD6140 can be configured with the chip powered up or down. In order to power the chip down, set pin POWER_DOWN (Pin 9) high. In order to power it up, set pin POWER_DOWN (Pin 9) low. Finally, an auxiliary amplifier used for biasing an external discrete LNA is provided with the AD6140. FREQUENCY PLAN The AD6140 and its modulator are designed for a specific frequency plan: a 6.144 MHz master clock, a 49.6 MHz first IF input, and a 192 kHz center frequency in the bandpass modulator. The local oscillator may use high-side or low-side injection. The specifications for the AD6140 are only valid for this frequency plan. Any deviation from this frequency plan may result in degradation of the specified performance. Furthermore, there are only specific frequency plans which will result in acceptable performance for most applications. To avoid problems, do not change the frequency plan. USING THE AD6140 In this section, we will examine a few areas of special importance and include a few general applications tips. As is true of any device operating in the IF frequency range, special care must be taken in PC board layout. The location of the particular grounding points must be considered, with the objective of minimizing any unwanted signal coupling. Specifically, care should be taken in the layout of the IF and LO signal paths as well as the data and clock digital bit-streams. Layout of these portions of the PC board require special attention in order to ensure that the high frequency portions of these signals do not couple into other signals in the system. In order to maintain balance in differential signal levels, be sure to keep short and equal length transmission lines. The power supplies should be decoupled to ensure a clean dc signal. Special care should be taken with respect to ensuring that the BUFFER_VDD is especially clean and at the appropriate levels since the output in-band noise floor is particularly sensitive to this supply. The IF input signal should be impedance matched and ac coupled. The impedance looking into the IF input pin is typically a 2.5 k resistance in parallel with a 12 pF capacitance. The 1 V reference signal should be regulated and filtered. The value of the BIAS_RESISTOR (Pin 16) is 39 k. The bias resistor sets the current consumption of the AD6140. Because the AD6140 was characterized with a 39 k bias resistor, this is the only value for which the AD6140 specifications are guaranteed. Maximum current consumption is measured when the AD6140 is operating at maximum gain. The AGC integration capacitor should be large enough to bypass any externally-generated noise on the internal AGC line to ground in addition to providing a path for the charging and discharging of the AGC current. In the Motorola ReFLEX chipset solution, this capacitor is 0.1 F. The AGC time constant is switch-selectable with the AGC_TC_SELECT pin (Pin 10). The AGC time constant has a typical current ratio of 56:1 when in the fast mode relative to slow mode. The nominal AGC current in the fast (high current) position is 2.8 A and in the slow (low current) position is 50 nA. The AGC time constant may be calculated from Equation 1. T= CV I (1) where T is the AGC time constant in seconds, C is the value of the AGC capacitor in Farads, V is the full-scale change in the AGC voltage, and I is the charging current in amperes. REV. 0 -7- AD6140 LEVEL DIAGRAM Motorola ReFLEX Transceiver Figure 10 shows a simplified block diagram of the AD6140 with the expected signal levels for the minimum gain configuration. LOCAL OSCILLATOR INPUT 49.792MHz -16.3 dBm REFERRED TO 50 MIXER POST AMPLIFIER DATA OUT 378mV p-p AT 192kHz PREAMPLIFIER IF INPUT f = 49.6MHz 60mV p-p MODULATOR MIXER AGC DETECTOR CIRCUIT Figure 10. Level Diagram LNA Tx/Rx SW 929-941MHz SC-4344-A SAW FILTER AGC 1 WATT 986-902MHz 2.4V HBT PA TRF9506 I/Q MODULATOR 49.6MHz XTAL FILTER IF DATA AD6140 A/D CLOCK IF DATA PROCESSOR SPI TO REFLEX CODEC 6.144MHz SAMPLING CLK MC145181 FREQUENCY SYNTHESIZER 76.8MHz REF CLK 2.8V DVDD MAX847 PWR MGT 2.7V AVDD PRIMARY BATTERY TRANSMIT POWER SOURCE Tx DATA Figure 11. ReFLEX Transceiver Block Diagram OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead SSOP (RS-20) 0.295 (7.50) 0.271 (6.90) 20 11 0.212 (5.38) 0.205 (5.21) PIN 1 1 10 0.311 (7.9) 0.301 (7.64) 0.078 (1.98) 0.068 (1.73) 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC 8 SEATING 0.009 (0.229) 0 PLANE 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) -8- REV. 0 PRINTED IN U.S.A. C3436-3-10/98 Figure 11 shows a block diagram of the Motorola ReFLEX chipset solution including the AD6140. As can be seen, the AD6140 accepts an IF input from a crystal filter at 49.6 MHz. The frequency synthesizer provides the 6.144 MHz clock, while the LO is also generated from the frequency synthesizer but is fed to the AD6140 via the I/Q modulator. The IF data output and the clock output both feed into the IF data processor. The LNA bias amplifier provides the AGC voltage for the first LNA in the receive path. The dc power is supplied from the power management chip. |
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